We first simulated and synthesized a FIR filter with 11 coefficients.
\\begin{table}[h]
\\centering
\\caption{FIR HLS Implementation Summary}
\\begin{tabular}{|c|c|c|c|c|c|c|c|c|}
\\hline
\\multirow{2}{*}{Clk (ns)} & \\multicolumn{2}{c|}{Clock Cycles} & \\multicolumn{5}{c|}{Utilization} & \\multirow{2}{*}{Throughput} \\\\
\\cline{2-8}
& Latency & Interval & BRAM & DSP & FF & LUT & URAM & \\\\
\\hline
6.912 & 21 & 22 & 0 & 3 & 1014 & 538 & 0 & 1/(22*6.912 ns) \\\\
& & & (0\\
*%) & (1\\%) & ($\\sim$0\\%) & (1\\%) & (0\\%) & $\\approx$ 6.55 MHz \\\\*
\\hline
\\end{tabular}
\\end{table}
Next, we simulated and synthesized a FIR filter with 128 coefficients.
\begin{table}[h] \centering \caption{FIR128 Baseline HLS Implementation Summary} \begin{tabular}{|c|c|c|c|c|c|c|c|c|} \hline \multirow{2}{}{Clk (ns)} & \multicolumn{2}{c|}{Clock Cycles} & \multicolumn{5}{c|}{Utilization} & \multirow{2}{}{Throughput} \\ \cline{2-8} & Latency & Interval & BRAM & DSP & FF & LUT & URAM & \\ \hline 6.912 & 135 & 136 & 3 & 1 & 755 & 503 & 0 & 1/(136*6.912 ns) \\ & & & (1\
%) & ($\sim$0\%) & ($\sim$0\%) & ($\sim$0\%) & (0\%) & $\approx$ 1.06 MHz \\
\hline \end{tabular} \end{table}
% Brief Report Section
\section{Comparison of FIR11 and FIR128 Baseline Implementations}
This section presents a comparison between the FIR11 and FIR128 baseline implementations synthesized using Vitis HLS. Tables 1 and 2 summarize the key performance metrics and resource utilization for both designs.
\subsection{Performance Analysis}
Both implementations achieve the same clock frequency of approximately 144.68 MHz (6.912 ns clock period). However, they differ significantly in terms of latency and throughput:
\begin{itemize} \item FIR11: Latency of 21 cycles, throughput of $\approx$ 6.55 MHz \item FIR128: Latency of 135 cycles, throughput of $\approx$ 1.06 MHz \end{itemize}
The FIR128 implementation has a longer latency due to the increased number of taps, resulting in a lower throughput compared to the FIR11 design.
\subsection{Resource Utilization}
Both designs demonstrate efficient resource utilization:
\begin{itemize} \item FIR11 uses slightly more DSP slices (3 vs. 1) and has higher FF and LUT usage. \item FIR128 requires more BRAM (3 vs. 0), likely for storing the increased number of coefficients. \item Both designs use minimal percentages of available resources, with most utilization rates below 1\
%.
\end{itemize}
We investigated how variable bitwidths affect resource usage and performance.
Performance did not change, [why? ]